/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __AXNU_H__
#define __AXNU_H__


#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif
#endif /* __cplusplus */

#include "ax.h"

typedef enum eiAXNU_STAT_CODE_E {
	AXNU_IDLE,
	AXNU_BUSY,
	AXNU_PAUSED,
	AXNU_STOPPED,
	AXNU_ERR,
} AXNU_STAT_CODE_E;

typedef enum eiAXNU_ERR_CODE_E {
	AXNU_OK = 0,
	AXNU_WAIT  = -1,
	AXNU_ERR_UNKNOWN = -2,
	AXNU_ERR_BUSY = -100,
	AXNU_ERR_CFG = -101,
	AXNU_ERR_CONFLICT = -103,
	AXNU_ERR_TIMEOUT = -203
} AXNU_ERR_CODE_E;

typedef struct eiAXNU_INFO_S {
	AXNU_STAT_INFO_S stat_info;
	AXNU_CTL_S clt_info;
	AXNU_STATUS_OUT_S stat_out;
	unsigned int nu_count;
	unsigned int nu_status;
} AXNU_INFO_S;

#define AX_BASE_ADDR         0x00000000 /* 0x01700000 */

/* ENU Registers */
#define NVX_TOP_VER           (AX_BASE_ADDR + 0x000)
#define NVX_TOP_FTR           (AX_BASE_ADDR + 0x004)
#define NVX_TOP_RST           (AX_BASE_ADDR + 0x010)
#define NVX_TOP_ADDR64G       (AX_BASE_ADDR + 0x014)
#define NVX_TOP_CLK_CTL       (AX_BASE_ADDR + 0x0A0)
#define NVX_TOP_SRC_SEL       (AX_BASE_ADDR + 0x0A4)
#define NVX_TOP_ADPLL_TUNE0   (AX_BASE_ADDR + 0x0A8)
#define NVX_TOP_ADPLL_TUNE1   (AX_BASE_ADDR + 0x0AC)
#define NVX_TOP_ADPLL_STAT    (AX_BASE_ADDR + 0x0B0)
#define NVX_TOP_ADPLL_FQMS    (AX_BASE_ADDR + 0x0B4)

/* ENU Registers */
#define NVX_OCM               (AX_BASE_ADDR + 0x104)
#define NVX_OCM_BASE          (AX_BASE_ADDR + 0x108)

#define NVX_CTL               (AX_BASE_ADDR + 0x110)
#define NVX_STAT0             (AX_BASE_ADDR + 0x118)
#define NVX_STAT1             (AX_BASE_ADDR + 0x11C)
#define NVX_CMDQ_INT_EN       (AX_BASE_ADDR + 0x120)
#define NVX_CMDQ_INT_PD       (AX_BASE_ADDR + 0x124)
#define NVX_CMDQ_INT_CLR      (AX_BASE_ADDR + 0x128)
#define NVX_INPUT_ADDR        (AX_BASE_ADDR + 0x130)
#define NVX_INTERNAL_ADDR     (AX_BASE_ADDR + 0x134)
#define NVX_OUTPUT_ADDR       (AX_BASE_ADDR + 0x138)
#define NVX_CMDQ_ADDR         (AX_BASE_ADDR + 0x13C)

#define NVX_CMDQ_INT_EN0     (AX_BASE_ADDR + 0x140)
#define NVX_CMDQ_INT_EN1     (AX_BASE_ADDR + 0x144)
#define NVX_CMDQ_INT_EN2     (AX_BASE_ADDR + 0x148)
#define NVX_CMDQ_INT_EN3     (AX_BASE_ADDR + 0x14C)

#define NVX_CMDQ_INT_PD0     (AX_BASE_ADDR + 0x150)
#define NVX_CMDQ_INT_PD1     (AX_BASE_ADDR + 0x154)
#define NVX_CMDQ_INT_PD2     (AX_BASE_ADDR + 0x158)
#define NVX_CMDQ_INT_PD3     (AX_BASE_ADDR + 0x15C)

#define NVX_CMDQ_INT_CLR0    (AX_BASE_ADDR + 0x160)
#define NVX_CMDQ_INT_CLR1    (AX_BASE_ADDR + 0x164)
#define NVX_CMDQ_INT_CLR2    (AX_BASE_ADDR + 0x168)
#define NVX_CMDQ_INT_CLR3    (AX_BASE_ADDR + 0x16C)

#define NVX_CMDQ_RSZCTL      (AX_BASE_ADDR + 0x170)
#define NVX_CMDQ_PAUSE0      (AX_BASE_ADDR + 0x180)
#define NVX_CMDQ_PAUSE1      (AX_BASE_ADDR + 0x184)
#define NVX_CMDQ_PAUSE2      (AX_BASE_ADDR + 0x188)
#define NVX_CMDQ_PAUSE3      (AX_BASE_ADDR + 0x18c)

#define NVX_FREQ_ADJ         (AX_BASE_ADDR + 0x1D4)
#define NVX_ADDR64_OFT       (AX_BASE_ADDR + 0x1D8)

#define NVX_PERF_CNT         (AX_BASE_ADDR + 0x1E4)
#define NVX_BW_STAT_EN       (AX_BASE_ADDR + 0x1E8)
#define NVX_BW_R_STAT        (AX_BASE_ADDR + 0x1EC)
#define NVX_BW_W_STAT        (AX_BASE_ADDR + 0x1F0)


#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* __cplusplus */

#endif
